The present invention relates to data processors, and more particularly to a data processor which is well suited to a symbol process such as character string data process.
As described in Japanese Patent Application Laid-open No. 87640/1978, a prior-art vector processor has handled as each vector element, data such as an integer or a floating point number which can be fetched at one time. This is because the prior-art vector processor has been used solely for the calculations of numerical values and has sufficed with the above function. The prior art has not taken into consideration an application to the field of a symbol process, that is, a case where each vector element is a character string, a list or the like of indefinite length.
The aforementioned prior art has had the problem that throughput lowers in a case where access of certain data needs to wait for the arrival of preceding data. This problem will now be briefly explained with reference to the drawings.
FIG. 9 shows an example of a vector operation in a symbol process. In the operation, two vectors X and Y are input, and a vector Z is output. Each element of the vector to be input consists of a tag part of 4 bytes and a key part of 12 bytes. In this operation, the key parts of the respective elements of the vectors X and Y are compared, and if they coincide, the pair of the tag parts of the respective elements is delivered as the element of the output vector Z, whereas if not, 0's are delivered (hereinbelow, this operation shall be called the "sequential search operation"). It is now assumed that a vector processor for executing the sequential search operation can read out data of 4 bytes at one time of fetch request. Then, 16.div.4=4 times of fetches are required for reading out one vector element.
A method shown in FIG. 10(a) is considered as a scheme for vector-processing the sequential search operation. Fetching and comparing the respective 4 bytes of the corresponding elements of input vectors from the left sides thereof are repeated for all the data of the vectors (numerals written in vector data in FIGS. 10(a)-10(c) denote the order of fetches). As depicted on the right side of FIG. 10(a), with this method, pipelining in which fetches and operations are performed in parallel is possible, and the process of the 4-byte data in each fetch unit is apparently completed in one machine cycle (MC).
The above method is excellent from the viewpoint of the pipeline implementation of the process, but it involves useless processing steps. For example, in the comparison between the key parts of elements X(0) and Y(0), non-coincidence is already found by the comparative operation of the first 4 bytes, namely, `id56` and `id23`. Accordingly, the comparative operations of the remaining 8 bytes, `0280051T` and `0183017A` are essentially unnecessary. Nevertheless, these unnecessary operations are also performed by the method illustrated in FIG. 10(a). This drawback becomes more conspicuous as the length of the elements is greater. As an expedient for avoiding the unnecessary operations, a vector processor based on a scheme shown in FIG. 10(b) has formerly been proposed by the same inventors as those of the present application (Japanese Patent Application No. 104543/1984). Herein, when coincidence/non-coincidence has been found after the comparison of 4 bytes in the key parts, the process is immediately shifted to the fetch of the next elements, and when not, succeeding data items in the key parts are fetched. With this method, data items to be subsequently fetched and operated are determined after the comparative operation, so that wasteful operations can be avoided. Since, however, elements to be subsequently fetched are determined according to the operated result in this method as depicted on the right side of FIG. 10(b), fetches and operations cannot be performed in parallel. That is, the pipeline implementation is impossible, and vacancies arise in the process.